(1) Field of the Invention
This invention relates generally to output drivers, and more particularly to high voltage digital output drivers.
(2) Description of the Prior Art
The growing integration density of VLSI circuits and the low-power requirements of complex signal processing applications, drives the use of deep-submicron technologies in modern IC's. Since these technologies imply low supply voltages, the design of high efficient power amplifiers and line drivers becomes extremely difficult in standard CMOS.
It is therefore a challenge to design a reliable and efficient high voltage output driver in standard CMOS technology on a single IC. In prior art different technologies such as smart power and various Bipolar-CMOS-DMOS (BCD) processes have been developed to solve the conflict of reducing voltages due to technology feature size with the requirements for operation at continued relatively high voltages. However the additional technology steps become rather expensive compared with a basic CMOS process.
There are various solutions known to address
Bert Serneels et al. (“A high voltage output driver in a 2.5 V 0.25 μm CMOS technology”, IEEE Journal of Solid-State Circuits, Vol. 40, No. 3, March 2005) describe the design of a high-voltage output driver in a digital 2.5 V 0.25 μm CMOS technology. The use of stacked devices with a self-biased cascade topology allows the driver to operate at three times the nominal supply voltage.
U.S. Patent Application Publication (2003/0189443 to Kunz et al.) proposes an output driver architecture that uses thin gate-oxide core and thin gate-oxide Drain-extended transistors that can directly interface with voltage supplies up to six times the normal rating of the transistor. A bias generator, level shifter and output stage are adapted to buffer an input signal with a voltage swing of less than the normal operating voltage of the transistors to an output signal with a voltage swing of up to approximately six times the normal operating voltage of the transistors. The bias generator is interfaced directly with a high voltage power supply and generates a bias voltage with a magnitude of less than the dielectric breakdown of the transistors internal to the level shifter and output stage. Further, the bias generator is adapted to sense the magnitude of the high voltage supply, and to automatically and continuously self-adjust the bias voltage in response to changes sensed in the magnitude of the high voltage supply such that the bias generator can be used for a continuous range of high voltage supplies up to 6 times the normal operating voltage of the transistors.
U.S. patent (U.S. Pat. No. 6,580,291 to Lutley) discloses an apparatus comprising a first circuit configured to generate a first portion of an output signal in response to (i) a first supply voltage and (ii) a pull-up signal and a second circuit configured to generate a second portion of said output signal in response to (i) a second supply voltage and (ii) a pulldown signal, wherein said first and second circuits are implemented with transistors that normally can only withstand said second supply voltage.
U.S. patent (U.S. Pat. No. 6,429,686 to Nguyen) discloses an output driver on an integrated circuit (IC) including at least one transistor that has a thicker gate oxide than other standard transistors in the IC. In one embodiment, the output driver includes two pull-up transistors. A first pull-up transistor has a thicker gate oxide than standard transistors on the IC to provide a wide range of output voltages on the pad. A second pull-up transistor has a standard, i.e. thin, gate oxide thickness to ensure a fast low-to-high voltage transition on the pad. The other transistors in the output driver have standard gate oxide thicknesses. Illustrative thicknesses include 150 Angstroms for the first pull-up transistor and 50 Angstroms for the second pull-up transistor.